As the size of features included in integrated circuit devices is reduced, the spacing between those features may be reduced. Voids or seams can occur if the gaps are incompletely filled, for example, with insulation layers. Voids and/or seams can be more likely when an aspect ratio of the gap (i.e., a ratio of the depth of the gap to the width of the gap opening) is increased.
FIGS. 1 to 3 are cross-sectional views that illustrate a conventional method of filling a gap. Referring to FIG. 1, a pattern is formed on a substrate 10 including gaps 14 that are subsequently filled by a material. For example, the pattern may be trenches, gate electrodes or interconnections. If the pattern includes trenches (as shown in FIG. 1), the trenches themselves can be considered to be the gaps 14 that are filled. On the other hand, if the pattern includes gate electrodes or the interconnections, spaces between the gate electrodes (or the interconnections) can be considered the gaps 14 that are filled.
Referring to FIG. 2, an isolation layer 18, such as a high-density plasma oxide layer or an undoped silicate glass (USG) layer, is deposited in the gaps 14. However, as shown in FIG. 2, voids 20a or seams 20b may occur in the gaps 14 if the aspect ratio of the gaps 14 is 8:1 or more.
Referring to FIG. 3, the insulation layer 18 containing the voids 20a or the seams 20b is planarized using, for example, chemical mechanical polishing methods or an etch back process. When the insulation layer 18 is planarized, some of the voids 20a and seams 20b may be exposed through an opening 20c in the surface.
Accordingly, remnants of a subsequently deposited conductive layer or other contaminant material may be deposited in the voids 20a and the seams 20b through the opening.